Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock, each cycle may consume power even when the logical value of the input is otherwise unchanged.
This may be appreciated by referring to FIG. 1 illustrating an exemplary two-input NAND dynamic logic gate. Dynamic logic 100 includes two inputs A and B coupled to a corresponding gate of N channel field effect transistors (NFETs) 101-102. During an evaluate phase (logic one) of clock 104, NFET 106 is turned ON, and if any of inputs A or B are a logic one, dynamic node 108 is pulled low (logic zero), and OUT transitions to a logic one via inverter 110. During the precharge phase (logic zero) of Clk 104, dynamic node 108 is precharged to a logic one via P channel field effect transistor (PFET) 112. Half-latch PFET 114 maintains the charge on dynamic node 108 through the evaluate phase unless both of inputs A and B are turned ON. Consequently, dynamic node 108 undergoes two discharge-precharge cycles. OUT similarly undergoes two discharge-precharge cycles, albeit with opposite phase. Because OUT is discharged during the precharge phase of dynamic node 108, even though the Boolean value of the logical function is “true”, the dynamic logic gate dissipates power even when the input signal states are unchanged. The NAND configuration of dynamic logic gate 100 forms and intermediate node 103 between NFETs 101 and 102. If both logic inputs A and B are a logic zero during the pre-charge phase then the dynamic node 108 “sees” only the capacitance of that node, however, if after the pre-charge phase input A transitions to a logic one then intermediate node 103 is coupled to the dynamic node 108. Thus, additional capacitance is added to the dynamic node which may cause it to droop do to load sharing. Logic trees in dynamic logic gates generally form intermediate nodes such as 103 which may similarly affect the dynamic node after the pre-charge phase.
Dynamic logic may use a footer NFET 106 or not. In the case the footer NFET 106 is not used, the inputs A and B must be timed to be valid during the evaluate phase of Clk 104. Regardless, dynamic circuits rely on the ability to pre-charge the dynamic node to a logic one state in advance of having valid logic inputs valid. In logic circuitry with a wide input fan-in, there are many parallel paths that may be coupled to the dynamic node by one or more select devices, leakage current may make it difficult to hold the logic state on the dynamic node until the start of the next evaluation cycle. This is especially true as device size decreases.
The sharp increase of leakage currents in scaled technologies severely limits the robustness of dynamic circuits, especially for high fan-in wide dynamic gates, commonly employed in the performance critical units of high-performance microprocessors. A strong keeper is necessary in the pre-charged state or after the completion of evaluation to compensate for the larger leakage current and to hold the right state at the dynamic node. Charge sharing is another major concern in dynamic circuits, which causes voltage drooped on the dynamic node, thus degrading the noise margins. A commonly used circuit technique to prevent the charge sharing effect consists of pre-charging the intermediate node (in the stack configuration) to Vdd during the pre-charge phase with a separate FEAT device. While the technique is quite effective, the intermediate node pre-charging device adds capacitance to the intermediate node (thus degrading its effectiveness in preventing charge sharing and circuit performance) and increases the circuit area.
There is, therefore, a need for a dynamic logic circuit design that adds minimum capacitance on the dynamic node while allowing intermediate nodes to be pre-charged along with the dynamic node.